Integrated circuits are typically fabricated as individual die which can be packaged. The integrated circuit die is fabricated from a wafer of silicon, or other suitable material, such that hundreds, or perhaps thousands, of individual die are simultaneously processed on one wafer. To insure operational integrity of each integrated circuit die, testing is performed while the circuits are still part of the wafer. In addition, internal voltage regulators and other operational circuitry such as fuses are adjusted while at the wafer level. FIG. 1 illustrates a top view of a typical integrated circuit wafer which is substantially round with one edge flattened or notched for orientation.
To test the integrated circuit die, a probe card is used which includes numerous electrical probes which are positioned during testing so that electrical contact locations provided on an integrated circuit die are accessed. Because each die contains extensive contact locations, sometimes up to one hundred or more locations, probe cards are very complicated and expensive. Further, to reduce the time required to test each integrated circuit die, probe cards are typically designed to probe several die at one time. A trade off is experienced between the cost of building and maintaining a probe card which probes a large number of die at one time, and the number of steps required during testing to physically contact each die on a wafer. At both extremes, a single complicated and expensive probe card could be designed to probe an entire wafer in one step, or a probe card which probes only one die at a time could be used by substantially increasing the number of steps. It is desired, therefore, to design and build probe cards which optimize the number of steps while maintaining an acceptable economic cost.
Currently, multi-die probe cards are designed using a "best guess" technique coupled with hand calculations which are prone to errors. To appreciate the deficiencies of present probe card designs, a brief explanation of a typical probe card design and usage is provided. To design a probe card matrix, numerous factors are taken into account, such as the physical size of each die and the number of probes required per die. As such, the layout of the probe card matrix is designed first. Once the probe card matrix is designed, manual calculations are performed to determine a sequence of steps required to test every die on a wafer. For example, a 2.times.3 probe card matrix (probes six die at one time) can be moved in numerous ways to cover an entire wafer of die without testing any die twice. Depending upon a wafer layout, a 1.times.6 or a 3.times.2 probe card may however require less steps to test an entire wafer.
A poorly designed, or non-optimized, probe card requires unnecessary time to probe a wafer, and thus is more expensive to operate. The time required to test a wafer is influenced by both fixed and variable sources. Each probe card step, or touchdown, requires tester process initiation steps, data recording time, and probe card movement time to move the probe card to different locations on the wafer. Total test time, therefore, can be reduced by minimizing the number of touchdowns for a wafer test. Further, by optimizing a probe card design, parallel operating functions can be exploited. That is, many test functions are run in a parallel mode to reduce overhead time and achieve a maximum utilization of hardware.
A probe card which is improperly designed to test too many die at one time can result in a sacrifice of hardware utilization. Too many sites, or an incorrect layout, result in extra setup and maintenance costs for probe pins that are seldom or never used. Further, incorrect layouts can actually cause more touchdowns than necessary. An increase in overhead time can also be experienced by tracking unused sites.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a probe card design method which optimizes the number of die probed per touchdown and minimizes the number of steps required to test a wafer.